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RELEASED DEVELOPMENT KIT BOARD USER MANUAL PMC-2001840
PM2352 FREEDM-32P672
ISSUE 1
DEVELOPMENT KIT BOARD USER MANUAL
PM7380
FREEDM-32P672
DEVELOPMENT KIT
USER MANUAL
RELEASED ISSUE 1: DECEMBER 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED DEVELOPMENT KIT BOARD USER MANUAL PMC-2001840
PM2352 FREEDM-32P672
ISSUE 1
DEVELOPMENT KIT BOARD USER MANUAL
CONTENTS 1 OVERVIEW.............................................................................................. 1 1.1 2 FEATURES ................................................................................... 1
HARDWARE CONFIGURATION ............................................................. 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 VOLTAGE SELECTION ................................................................ 4 SYSCLK JUMPER SETTING ........................................................ 5 JUMPER SETTING FOR RMVCK[3:0] PROVISION..................... 5 JUMPER SETTING FOR TMVCK[3:0] PROVISION ..................... 6 JUMPER SETTINGS FOR TMV8DC, RMV8DC, TMV8FPC AND RMV8FPC PROVISION ............................................................... 8 JUMPER SETTINGS FOR TFP8B AND RFP8B ........................... 9 JUMPER SETTINGS FOR RFPB[3:0]......................................... 10 JUMPER SETTINGS FOR TFPB[3:0] ..........................................11 JUMPER SETTINGS FOR SELECTION OF RCLK[2:0] AND TCLK[2:0] .................................................................................... 12 JUMPER SETTINGS FOR ENABLING OF RCLK[15:0] ............. 13 JUMPER SETTINGS FOR ENABLING OF RCLK[31:16] ........... 15 JUMPER SETTINGS FOR ENABLING OF TCLK[15:0] .............. 17 JUMPER SETTINGS FOR ENABLING OF TCLK[31:16] ............ 18 JUMPER SETTINGS FOR DATA LOOPBACK ON LINKS 2 THROUGH 31 ............................................................................. 20 JUMPER SETTINGS FOR DATA LOOPBACK/CROSS-CONNECT ON LINKS 0 AND 1 ..................................................................... 21 JUMPER SETTINGS FOR BERT EMULATION .......................... 22 PLACEMENT OF OSCILLATORS IN THE SOCKETS................ 23
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CONFIGURATIONS FOR THE TEST CASES ....................................... 25 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 CONFIGURATION FOR PCI INTERFACE TEST........................ 25 CONFIGURATION FOR UNCHANNELIZED T1 LOOPBACK MODE.......................................................................................... 26 CONFIGURATION FOR UNCHANNELIZED E1 LOOPBACK MODE.......................................................................................... 28 CONFIGURATION FOR 16 T1/ 16 E1 UNCHANNELIZED LOOPBACK MODE..................................................................... 31 CONFIGURATION FOR UNCHANNELIZED 52 MBIT/S............. 33 CONFIGURATION FOR UNCHANNELIZED MIXED DS3/T1/E1 DATA LOOPBACK....................................................................... 35 CONFIGURATION FOR UNCHANNELIZED 2.048 MBIT/S H-MVIP DATA LOOPBACK....................................................................... 38 CONFIGURATION FOR UNCHANNELIZED 8.192 MBIT/S H-MVIP DATA LOOPBACK....................................................................... 40 BERT SIGNAL VERIFICATION ................................................... 41
4
HOW TO PROCEED WITH THE TEST CASES .................................... 44
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LIST OF FIGURES FIGURE 1 FREEDM-32P672 DEVELOPMENT KIT BOARD DIAGRAM ....... 3 FIGURE 2 3.3V SELECTION HEADER (P16)................................................... 4 FIGURE 3 LEDS ON THE FREEDM-32P672 DEVELOPMENT KIT.............. 4 FIGURE 4 JUMPER SETTING FOR SYSCLK (P3) .......................................... 5 FIGURE 5 JUMPER SETTINGS FOR RMVCK[3:0] (P5). ................................. 6 FIGURE 6 JUMPER SETTING FOR TMVCK[3:0] (P6). .................................... 7 FIGURE 7 JUMPER SETTINGS FOR ENABLING OF RMV8FPC, TMV8FPC, TMV8DC, AND RMV8DC (P4)............................................................................ 9 FIGURE 8 JUMPER SETTINGS FOR RFP8B AND TFP8B (P9) ...................... 9 FIGURE 9 JUMPER SETTINGS FOR RFPB[3:0] (P8) ................................... 10 FIGURE 10JUMPER SETTINGS FOR TFPB[3:0] (P1).....................................11 FIGURE 11 JUMPER SETTINGS FOR SELECTION OF RCLK[2:0] AND TCLK[2:0] (P7).................................................................................................. 13 FIGURE 12JUMPER SETTINGS FOR ENABLING OF RCLK[15:0] (P12) ...... 14 FIGURE 13JUMPER SETTINGS FOR ENABLING OF RCLK[31:16] (P11)..... 16 FIGURE 14JUMPER SETTINGS FOR ENABLING OF TCLK[15:0] (P13)....... 17 FIGURE 15JUMPER SETTINGS FOR TCLK[31:16] (P14).............................. 19 FIGURE 16JUMPER SETTINGS FOR DATA LOOPBACK ON LINKS 2 TO 3121 FIGURE 17JUMPER SETTINGS FOR LOOPBACK/CROSS-CONNECT ON LINKS 0 AND 1 (P2) ......................................................................................... 22 FIGURE 18JUMPER SETTINGS FOR BERT DATA EMULATION (P15) ......... 22 FIGURE 19JUMPER SETTINGS FOR BERT CLOCK EMULATION (P7)........ 23
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LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 JUMPER SETTING FOR SYSCLK .................................................. 5 JUMPER SETTINGS FOR RMVCK[3:0].......................................... 6 JUMPER SETTING FOR TMVCK[3:0]............................................. 7
TABLE 4 JUMPER SETTINGS FOR ENABLING OF RMV8FPC, TMV8FPC, TMV8DC, AND RMV8DC.................................................................................... 9 TABLE 5 TABLE 6 TABLE 7 JUMPER SETTINGS FOR RFP8B AND TFP8B.............................. 9 JUMPER SETTINGS FOR RFPB[3:0] ............................................11 JUMPER SETTINGS FOR TFPB[3:0].............................................11
TABLE 8 JUMPER SETTINGS FOR SELECTION OF RCLK[2:0] AND TCLK[2:0] ........................................................................................13 TABLE 9 JUMPER SETTINGS FOR ENABLING OF RCLK[15:0] ................ 14
TABLE 10 JUMPER SETTINGS FOR ENABLING OF RCLK[31:16] .............. 15 TABLE 11 JUMPER SETTINGS FOR TCLK[15:0].......................................... 18 TABLE 12 JUMPER SETTINGS FOR ENABLING TCLK[31:16]..................... 18 TABLE 13 JUMPER SETTINGS FOR DATA LOOPBACK ON LINKS 2 THROUGH 31................................................................................................... 20 TABLE 14 JUMPER SETTINGS FOR LOOPBACK/CROSS-CONNECT ON LINKS 0 AND 1 ................................................................................................. 22 TABLE 15 JUMPER SETTINGS FOR BERT CLOCK EMULATION ............... 23 TABLE 16 OSCILLATOR PLACEMENT IN SOCKETS ................................... 23 TABLE 17 CONFIGURATION FOR THE PCI INTERFACE TEST .................. 25 TABLE 18 CONFIGURATION FOR SIMULTANEOUS LOOPBACK OF E1 DATA ON 32 LINKS .................................................................................................... 29 TABLE 19 CONFIGURATION FOR 16 T1/E1 UNCHANNELIZED LOOPBACK 31
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TABLE 20 SIMULTANEOUS LOOPBACK OF UNCHANNELIZED 52 MBIT/S DATA ON LINKS 0 THROUGH 2 ...................................................................... 33 TABLE 21 SIMULTANEOUS LOOPBACK OF UNCHANNELIZED MIXED DS3/T1/E1 DATA .............................................................................................. 35 TABLE 22 CONFIGURATION FOR UNCHANNELIZED 2.048 MBIT/S H-MVIP DATA LOOPBACK ............................................................................................ 38 TABLE 23 CONFIGURATION FOR UNCHANNELIZED 8.192 MBIT/S H-MVIP DATA LOOPBACK ............................................................................................ 40 TABLE 24 CONFIGURATION FOR BERT SIGNAL VERIFICATION TEST .... 42
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OVERVIEW The FREEDM-32P672 Development Kit consists of an add-on PCI card that can be used to test the functionality of the FREEDM-32P672 chip. The PCI card consists of all the necessary components used for testing the various functions of the FREEDM-32P672 device. This document provides the necessary information for configuring the FREEDM-32P672 Development Kit Board Rev 2.0. jumper settings.
1.1
Features * The Development Kit supports a 33/66 MHz, 32 bit Peripheral Component Interconnect (PCI) 2.1 compliant bus for configuration, monitoring and transfer of packet data. The Development Kit supports both unchannelized H-MVIP as well as nonH-MVIP traffic. Channelized T1/E1 traffic on the 32 links is not directly supported since there is no provision for gapping of the link clocks. Channelized H-MVIP mode is not directly supported since the frame pulses are not generated on the Development Kit card. Channelized T1/E1 operation can be supported only with an external gapped clock (i.e. gapped clock from an external source). Channelized H-MVIP mode can be supported with external frame pulses and frame pulse clocks.
*
*
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RELEASED DEVELOPMENT KIT BOARD USER MANUAL PMC-2001840
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HARDWARE CONFIGURATION Jumper settings are used to configure the Development Kit board for various modes of operation. The supported modes include: * * * * * Unchannelized T1 mode Unchannelized E1 mode Unchannelized 52 MHz mode Unchannelized 2.048 Mbit/s H-MVIP mode Mixed mode
For non-H-MVIP modes, only the following configurations can be achieved using jumper settings: * * * * * 32 T1 links 32 E1 links 16 T1 links and 16 E1 links 3 DS-3/unchannelized 52 Mbit/s links Mixed mode - 1 DS-3 link and T1/E1 links
With external gapped clock/frame pulse signals, channelized non H-MVIP as well as H-MVIP mode can be supported. This includes channelized 8 Mbit/s H-MVIP mode, for which an external frame pulse as well as frame pulse clocks are required. Note that the supplied software does not include support for includes channelized 8 Mbit/s H-MVIP mode. This section gives a detailed description of the jumper settings on the various headers. Figure 1 represents the block diagram for the FREEDM-32P672 development kit board.
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Figure 1
FREEDM-32P672 Development Kit Board Diagram
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2.1
Voltage Selection The FREEDM-32P672 requires a 3.3 V source. The user has the option of using either the 3.3 V provided by the PCI connector or a board regulated 3.3 V source. The jumper settings for achieving these configurations are shown in Figure 2.
REG 3_3 REG 3_3
PCI 3_3 A
PCI 3_3 B
Figure 2
3.3V Selection Header (P16).
There are three LED's near the upper right corner on the topside of the Development Kit board. Plugging the Development Kit board into the PCI slot causes the green LED (indicating 5 V) to light upon power up. The two other LED's will light only if the 3.3 V source is selected. Figure 3 shows the location of these LED's on the board.
Figure 3
LED's on the FREEDM-32P672 Development Kit
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RELEASED DEVELOPMENT KIT BOARD USER MANUAL PMC-2001840
PM2352 FREEDM-32P672
ISSUE 1
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2.2
SYSCLK Jumper Setting The SYSCLK input of the FREEDM-32P672 chip can be provided with either a 40 MHz clock from an oscillator, or the PCICLKO clock output of the FREEDM32P672 chip (provided that a 33 MHz PCI bus is in use). The jumper settings on header P3 to achieve these configurations are shown in Figure 4. The jumper settings are also listed in Table 1.
A B C A B C
SYSCLK <= 40 MHz
SYSCLK <= PCICLKO
Figure 4 Table 1 HEADER P3 P3
Jumper setting for SYSCLK (P3) Jumper setting for SYSCLK JUMPER SETTING Shorting jumper over pins A and B Shorting jumper over pins B and C CONFIGURATION SYSCLK from oscillator SYSCLK from PCICLKO
Note: Pins B and C should only be shorted when the card is installed in a system with a 33 MHz PCI bus. 2.3 Jumper setting for RMVCK[3:0] provision Each of the four RMVCK inputs to the FREEDM-32P672 chip can be configured independently. Each RMVCK input to the FREEDM-32P672 chip can either be grounded or provided with a 4.096 MHz clock from an oscillator. The jumper settings on header P5 to achieve these configurations are as shown in Figure 5. The jumper settings are also listed in Table 2. In non-H-MVIP or 8.192 Mbit/s H-MVIP mode, RMVCK[3:0] should be grounded. To ground RMVCK[n] (0 n 3), pin B-n should be shorted to pin C-n on header P5. 4.096 MHz clock from an oscillator can be provided to RMVCK[n] by shorting pins B-n and A-n. The jumper settings in Figure 5 (a) correspond to 4.096 MHz on RMVCK[3:0], whereas the jumper settings in Figure 5(b) correspond to grounded RMVCK[3:0].
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3
2
1
0 A B C
3
2
1
0 A B C
RMVCK[3:0] <= 4.096 MHz
RMVCK[3:0] <= GND
Note : Numbers written above the header represent the link groups. Figure 5 Table 2 HEADER P5 Jumper settings for RMVCK[3:0] (P5). Jumper settings for RMVCK[3:0] JUMPER SETTINGS Shorting jumper over pins A-n and B-n (0 n 3) CONFIGURATION 4.096 MHz input to RMVCK[n]. (0 n 3) Unchannelized 2.048 Mbit/s HMVIP mode . P5 Shorting jumper over pins C-n and B-n (0 n 3) RMVCK[n] grounded. (0 n 3) Non - 2.048 Mbit/s H-MVIP mode. Note : Each of the RMVCK inputs can be configured independent of the other RMVCK inputs. For channelized 2.048 Mbit/s H-MVIP mode, external RMVCK should be provided by means of a wire to board connector plugged into pins of rows B and C on header P5. The ground plugs on the wire to board connector should mate with the ground pins (row C) on header P5. 2.4 Jumper setting for TMVCK[3:0] provision Similar to RMVCK, each of the four TMVCK inputs to the FREEDM-32P672 device can be configured independently. Each TMVCK input to the FREEDM-
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32P672 device can either be grounded or provided with a 4.096 MHz clock from an oscillator. The jumper settings on header P6 to achieve these configurations are shown in Figure 6. The jumper settings are also listed in Table 3. In non-H-MVIP or 8.192 Mbit/s H-MVIP mode, TMVCK[3:0] should be grounded. To ground TMVCK[n] (0 n 3), pin B-n should be shorted to pin C-n on header P6. The 4.096 MHz clock from an oscillator can be provided to TMVCK[n] by shorting pins B-n and A-n. The jumper settings in Figure 6(a) correspond to 4.096 MHz on TMVCK[3:0], whereas the jumper settings in Figure 6(b) correspond to grounded TMVCK[3:0].
0 1 2 3 A B C TMVCK[3:0] <= 4.096 MHz TMVCK[3:0] <= GND 0 1 2 3 A B C
Note : Numbers written above the header represent the link groups. Figure 6 Table 3 HEADER P6 Jumper setting for TMVCK[3:0] (P6). Jumper setting for TMVCK[3:0] JUMPER SETTINGS Shorting jumper over pins A-n and B-n (0 n 3) CONFIGURATION 4.096 MHz input to TMVCK[n]. (0 n 3) Unchannelized 2.048 Mbit/s HMVIP mode . P6 Shorting jumper over pins C-n and B-n (0 n 3) TMVCK[n] grounded. (0 n 3) Non - 2.048 Mbit/s H-MVIP mode.
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Note : Each of the TMVCK inputs can be configured independent of the other TMVCK inputs. For channelized 2.048 Mbit/s H-MVIP mode, external TMVCK is provided by means of a wire to board connector plugged into pins of rows B and C on header P6. The ground plugs on the wire to board connector should mate with the ground pins (row C) on header P6. 2.5 Jumper settings for TMV8DC, RMV8DC, TMV8FPC and RMV8FPC provision The RMV8DC input to the FREEDM-32P672 chip can either be grounded or provided with a 16.384 MHz clock from an external source by means of a wire to board connector. Similarly, the TMV8DC input to the FREEDM-32P672 chip can either be grounded or provided with a 16.384 MHz clock from an external source. The RMV8FPC and TMV8FPC pins of the chip can either be grounded or provided with frame pulse clock signals from an external source. The jumper settings on header P4 to achieve these configurations are shown in Figure 7. They are also listed in Table 4. In non-H-MVIP or 2.048 Mbit/s H-MVIP mode, TMV8DC and RMV8DC should be grounded. To ground these inputs, pins in row D should be shorted to corresponding pins in row C on header P4. Also, RMV8FPC and TMV8FPC should be grounded by shorting pins in row B to the corresponding pins in row A. For 8.192 Mbit/s H-MVIP mode, external TMV8DC, RMV8DC, TMV8FPC and RMV8FPC should be provided by means of a wire to board connector plugged into pins on header P4. The ground plugs on the wire to board connector should mate with the ground pins (rows A and C) on header P4. Note that this mode is not presently supported in software.
GND RMV8FPC GND RMV8DC
A GND B TMV8FPC C GND D RMV8DC = GND TMV8DC = GND RMV8FPC = GND TMV8FPC = GND TMV8DC
A B C D RMV8DC = EXTERNAL TMV8DC = EXTERNAL RMV8FPC = EXTERNAL TMV8FPC = EXTERNAL
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Figure 7 Jumper settings for enabling of RMV8FPC, TMV8FPC, TMV8DC, and RMV8DC (P4) Table 4 Jumper settings for enabling of RMV8FPC, TMV8FPC, TMV8DC, and RMV8DC HEADER P4 JUMPER SETTING Pins in row A shorted to corresponding pins in row B Pins in row C shorted to corresponding pins in row D Wire to board connector plugged into pins on header P4. CONFIGURATION TMV8DC and RMV8DC grounded. TMV8FPC and RMV8FPC grounded. Non-8.192 Mbit/s H-MVIP mode. 16.384 MHz clock provided to RMV8DC and TMV8DC. 4.096 MHz clock provided to RMV8FPC and TMV8FPC.
P4
Note : The falling edges of RMV8FPC and TMV8FPC should be aligned respectively with the falling edges of RMV8DC and TMV8DC, with no more than 10 ns skew. 2.6 Jumper settings for TFP8B and RFP8B TFP8B and RFP8B should be pulled down to ground when unchannelized 8.192 Mbit/s H-MVIP mode is not used. Both TFP8B and RFP8B should be pulled high for unchannelized 8.192 Mbit/s H-MVIP mode. The jumper settings on header P9 to achieve this configuration are shown in Figure 8. They are also listed in Table 5.
TFP8B RFP8B B C A RFP8B <= GND TFP8B <= GND Non-8.192 Mbit/s H-MVIP Mode B C A RFP8B <= 3.3V TFP8B <= 3.3V Unchannelized 8.192 Mbit/s H-MVIP Mode
Figure 8 Table 5 HEADER P9
Jumper settings for RFP8B and TFP8B (P9) Jumper settings for RFP8B and TFP8B JUMPER SETTING Pins in column C shorted to CONFIGURATION TFP8B and RFP8B pulled high
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P9
corresponding pins in column B Pins in column A shorted to corresponding pins in column B
(3.3 V). TFP8B and RFP8B grounded. Non - 8.192 Mbit/s H-MVIP mode.
For 8.192 Mbit/s H-MVIP mode, external TFP8B and RFP8B have to be provided by means of a wire to board connector plugged into pins of columns A and B on header P9. The ground plugs on the wire to board connector should mate with the ground pins (column A) on header P9. 2.7 Jumper settings for RFPB[3:0] RFPB[3:0] should be pulled down to ground when unchannelized 2.048 Mbit/s HMVIP mode is not used. If the links in one or more link groups are used for unchannelized 2.048 Mbit/s H-MVIP mode, RFPB inputs for these link groups should be pulled high. RFPB for each link group can be configured independently. The jumper settings on header P8 to achieve these configurations are listed in Figure 9. They are also listed in Table 6.
0 1 2 3 C B A 0 1 2 3 C B A
RFPB <= 3.3V
RFPB[3:0] <= GND
Note : RFPB for each link group can be independently configured with a single shorting jumper. Figure 9 Jumper settings for RFPB[3:0] (P8)
For channelized 2.048 Mbit/s H-MVIP mode, external RFPB[3:0] has to be provided by means of a wire to board connector plugged into pins of columns A and B on header P8. The ground plugs on the wire to board connector should mate with the ground pins (column A) on header P8.
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Table 6 HEADER P8
Jumper settings for RFPB[3:0] JUMPER SETTINGS Pin A-n shorted to pin B-n (0 n 3) Pin C-n shorted to pin B-n (0 n 3) CONFIGURATION RFPB[n] grounded. (0 n 3) Non- 2.048 Mbit/s H-MVIP mode. RFPB[n] pulled high (3.3 V). (0 n 3) Unchannelized 2.048 Mbit/s H-MVIP mode on link group n.
P8
2.8
Jumper settings for TFPB[3:0] TFPB[3:0] should be pulled down to ground when unchannelized 2.048 Mbit/s HMVIP mode is not used. If the links in one or more link groups are used for unchannelized 2.048 Mbit/s H-MVIP mode, the TFPB inputs for these link groups should be pulled high. TFPB for each link group can be configured independently. The jumper settings on header P1 to achieve these configurations are listed in Figure 10. They are also listed in Table 7.
0 1 2 3 A B C TFPB[3:0] <= GND TFPB[3:0] <= 3.3V 0 1 2 3 A B C
Note : TFPB for each link group can be independently configured with a single shorting jumper. Figure 10 Table 7 HEADER P1 Jumper settings for TFPB[3:0] (P1) Jumper settings for TFPB[3:0] JUMPER SETTINGS Pin A-n shorted to pin B-n (0 n 3) Pin C-n shorted to CONFIGURATION TFPB[n] grounded . (0 n 3) Non- 2.048 Mbit/s H-MVIP mode. TFPB[n] pulled high (3.3 V).
P1
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HEADER
JUMPER SETTINGS pin B-n (0 n 3)
CONFIGURATION (0 n 3) Unchannelized 2.048 Mbit/s H-MVIP mode on link group n.
For channelized 2.048 Mbit/s H-MVIP mode, external TFPB[3:0] has to be provided by means of a wire to board connector plugged into pins of rows A and B on header P1. The ground plugs on the wire to board connector should mate with the ground pins (row A) on header P1. 2.9 Jumper settings for selection of RCLK[2:0] and TCLK[2:0] In non-H-MVIP mode, RCLK[2:0] and TCLK[2:0] can be set to either T1/E1 clock frequency or DS-3/52 MHz clock frequency. Jumper settings on header P7 to make this selection are listed in Table 8. Figure 11 shows how the jumpers are used on header P7.
RCL52(0-2) C B A R0 R1 R2 RBCLK T0 T1 T2 TBCLK TCL52(0-2)
A) T1/E1 Frequency on RCLK[2:0] and TCLK[2:0]
RCL52(0-2) C B A R0 R1 R2 RBCLK T0 T1 T2 TBCLK TCL52(0-2)
B) DS-3/52 MHz Frequency on RCLK[2:0] and TCLK[2:0]
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Figure 11
Jumper settings for selection of RCLK[2:0] and TCLK[2:0] (P7)
Note : The numbers T0, T1 and T2, corresponding to TCL52 (0-2) and R0, R1 and R2, corresponding to RCL52 (0-2), shown in Figure 11, respectively represent transmit and receive links 0, 1 and 2. Table 8 HEADER P7 P7 P7 P7 Jumper settings for selection of RCLK[2:0] and TCLK[2:0] JUMPER SETTINGS Pin A-Rn shorted to pin B-Rn (0 n 2) under RCL52 (0-2) label Pin C-Rn shorted to pin B-Rn (0 n 2) under RCL52 (0-2) label Pin A-Tn shorted to pin B-Tn (0 n 2) under TCL52 (0-2) label Pin C-Tn shorted to pin B-Tn (0 n 2) under TCL52 (0-2) label CONFIGURATION DS-3/52 MHz frequency on RCLK[2:0] T1/E1 frequency on RCLK[2:0] DS-3/52 MHz frequency on TCLK[2:0] T1/E1 frequency on TCLK[2:0]
Note : Each RCLK or TCLK selection can be configured independently. 2.10 Jumper settings for enabling of RCLK[15:0] RCLK[15:0] should be grounded when unchannelized H-MVIP mode is used on links 0 through 15. If one or more links from 0 through 15 is used for receiving non-H-MVIP traffic, the corresponding receive link clocks (i.e. RCLK[n] where 0 n 15 ) should be enabled. The jumper settings on header P12 for enabling RCLK[15:0] are listed in Table 9. Figure 12 shows the jumper settings for enabling all 16 receive link clocks from RCLK[15] through RCLK[0].
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0 1 2 3 4 5 6 7 13 10 15 14 12 11 8 9 A B C A B C
0 1 2 3 4 5 6 7 13 10 15 14 12 11 8 9
RCLK[2:0] <= T1/E1/DS-3/52 MHz RCLK[15:3] <= T1/E1 RCLK[15:0] enabled (non H-MVIP Mode)
RCLK[15:0] <= GND RCLK[15:0] grounded (H-MVIP Mode)
Note : The pins for links from 0 through 15 are not in sequential order. Each of the RCLK inputs to FREEDM-32P672 chip can be independently enabled. Figure 12 Jumper settings for enabling of RCLK[15:0] (P12)
Table 9 HEADER P12
Jumper settings for enabling of RCLK[15:0] JUMPER SETTING Pin A-n shorted to pin B-n (0 n 15) Pin C-n shorted to pin B-n (0 n 15) CONFIGURATION RCLK[n] connected to FREEDM-32P672 (0 n 15) RCLK[n] grounded (0 n 15)
P12
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PM2352 FREEDM-32P672
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For channelized non-H-MVIP mode, externally gapped RCLK[15:0] should be provided by means of a wire to board connector plugged into pins of rows B and C on header P12. The ground plugs on the wire to board connector should mate with the ground pins (row C) on header P12. 2.11 Jumper settings for enabling of RCLK[31:16] RCLK[31:16] should be grounded when unchannelized H-MVIP mode is used on links 16 through 31. If one or more links from 16 through 31 are used for receiving non-H-MVIP traffic, the corresponding receive link clocks (i.e. RCLK[n] where 16 n 31 ) should be enabled. The jumper settings on header P11 for enabling RCLK[31:16] are listed in Table 10. Figure 13 shows the jumper settings for enabling all 16 receive link clocks from RCLK[31] through RCLK[16]. Table 10 Jumper settings for enabling of RCLK[31:16] CONFIGURATION RCLK[n] connected to FREEDM32P672 (16 n 31) RCLK[n] grounded (16 n 31)
HEADER JUMPER SETTING P11 Pin A-n shorted to pin B-n (16 n 31) P11 Pin C-n shorted to pin B-n (16 n 31)
For channelized non-H-MVIP mode, externally gapped RCLK[31:16] should be provided by means of a wire to board connector plugged into pins of rows B and C on header P11. The ground plugs on the wire to board connector should mate with the ground pins (row C) on header P11.
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16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A B C A B C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RCLK[31:16] <= T1/E1 Non H-MVIP Mode
RCLK[31:16] grounded (H-MVIP Mode)
Note : Each of the RCLK inputs to FREEDM-32P672 chip can be independently enabled. Figure 13 Jumper settings for enabling of RCLK[31:16] (P11)
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2.12
Jumper settings for enabling of TCLK[15:0] TCLK[15:0] should be grounded when unchannelized H-MVIP mode is used on links 0 through 15. If one or more links from 0 through 15 is used for transmitting non-H-MVIP traffic, the corresponding transmit link clocks (i.e. TCLK[n] where 0 n 15 ) should be enabled. The jumper settings on header P13 for enabling TCLK[15:0] are listed in Table 11. Figure 14 shows the jumper settings for enabling all 16 transmit link clocks from TCLK[15] through TCLK[0].
2 1 0 3 5 4 6 7 8 9 10 12 11 14 13 15 A B C A B C 2 1 0 3 5 4 6 7 8 9 10 12 11 14 13 15
TCLK[2:0] <= T1/E1/DS-3/52 MHz TCLK[15:3] <= T1/E1 TCLK[15:0] enabled (Non H-MVIP Mode)
TCLK[15:0] <= GND TCLK[15:0] grounded (H-MVIP Mode)
Note : The pins for links 0 through 15 are not in sequential order. Each of the TCLK inputs to FREEDM-32P672 chip can be independently enabled. Figure 14 Jumper settings for enabling of TCLK[15:0] (P13)
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PM2352 FREEDM-32P672
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Table 11
Jumper settings for TCLK[15:0] CONFIGURATION TCLK[n] connected to FREEDM32P672 (0 n 15) TCLK[n] grounded (0 n 15)
HEADER JUMPER SETTING P13 Pin A-n shorted to pin B-n (0 n 15) P13 Pin C-n shorted to pin B-n (0 n 15)
For channelized non-H-MVIP mode, externally gapped TCLK[15:0] should be provided by means of a wire to board connector plugged into pins of rows B and C on header P13. The ground plugs on the wire to board connector should mate with the ground pins (row C) on header P13. 2.13 Jumper settings for enabling of TCLK[31:16] TCLK[31:16] should be grounded when unchannelized H-MVIP mode is used on links 16 through 31. If one or more links from 16 through 31 are used for transmitting non-H-MVIP traffic, the corresponding transmit link clocks (i.e. TCLK[n] where 16 n 31 ) should be enabled. The jumper settings on header P14 for enabling TCLK[31:16] are listed in Table 12. Figure 15 shows the jumper settings for enabling all 16 transmit link clocks from TCLK[31] through TCLK[16]. For channelized non-H-MVIP mode, externally gapped TCLK[31:16] should be provided by means of a wire to board connector plugged into pins of rows B and C on header P14. The ground plugs on the wire to board connector should mate with the ground pins (row C) on header P14. Table 12 Jumper settings for enabling TCLK[31:16] CONFIGURATION TCLK[n] connected to FREEDM-32P672 (16 n 31) TCLK[n] grounded (16 n 31)
HEADER JUMPER SETTING P14 Pin A-n shorted to pin B-n (16 n 31) P14 Pin C-n shorted to pin B-n (16 n 31)
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16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A B C A B C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TCLK[31:16] <= T1/E1 TCLK[15:0] enabled (Non H-MVIP Mode)
TCLK[15:0] grounded (H-MVIP Mode)
Figure 15
Jumper settings for TCLK[31:16] (P14)
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2.14
Jumper settings for Data loopback on links 2 through 31 Data loopback can be performed on a per link basis on links 2 through 31. The jumper settings for loopback on these links, are listed in Table 13. Figure 16 shows the jumper settings for loopback on all the links from 2 to 31. Table 13 Jumper settings for data loopback on links 2 through 31 CONFIGURATION Loopback on link `n' ( where 16 n 31) Loopback on link `n' ( where 2 n 15)
HEADER JUMPER SETTING P10 Pins in row `n' shorted with each other ( where 16 n 31) P15 Pins in row `n' shorted with each other ( where 2 n 15)
Note : Loopback can be performed on any link, independent of the other links. Pins on headers P10 and P15, corresponding to link `n' (where 2 n 31), need not be shorted if loopback is not to be performed on link `n'.
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P10 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GND TBD
P15 GND RBD 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Loopback on links 16 to 31
Loopback on links 2 to 15
Figure 16 2.15
Jumper settings for data loopback on links 2 to 31
Jumper settings for Data loopback/cross-connect on links 0 and 1 Placement of shorting jumpers over header P2 result in configuration of either loopback or cross-connect of data on links 0 and 1. This is shown in Figure 17. The jumper settings are also listed in Table 14.
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TD0 RD0
RD1 TD1
TD0 RD0
RD1 TD1
Simultaneous Cross Connect
Simultaneous Loopback
Figure 17
Jumper settings for loopback/cross-connect on links 0 and 1 (P2) Jumper settings for loopback/cross-connect on links 0 and 1 CONFIGURATION Cross-connect on links 0 and 1 Loopback on links 0 and 1
Table 14
HEADER JUMPER SETTING P2 TD0 shorted to RD1, TD1 shorted to RD0 P2 TD0 shorted to RD0, TD1 shorted to RD1 2.16
Jumper settings for BERT Emulation Link 2 is used to emulate the BERT interface. To emulate BERT interface, link 2 should act as the source of TBD data, and at the same time, receive data on RBD output of FREEDM-32P672 chip. RBCLK and TBCLK are respectively shorted to RCLK[2] and TCLK[2]. The jumper settings on headers P15 and P7 for BERT Emulation are listed in Table 15 and are also shown in Figure 18 and Figure 19.
GND TBD TD2 TD3 TD15 GND RBD RD2 RD3 RD15
Figure 18
Jumper settings for BERT data emulation (P15)
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RCL52(0-2) C B A 0 1 2 RBCLK 0 1
TCL52(0-2)
2 TBCLK
Figure 19 Table 15
Jumper settings for BERT Clock Emulation (P7). Jumper settings for BERT Clock Emulation CONFIGURATION BERT data emulation RBCLK shorted to RCLK[2] TBCLK shorted to TCLK[2]
HEADER JUMPER SETTING P15 TD2 shorted to TBD, RD2 shorted to RBD P7 Pin B2 (under RCL52(0-2) ) shorted to RBCLK. P7 Pin B2 (under TCL52(0-2) ) shorted to TBCLK. 2.17 Placement of oscillators in the sockets
Table 16 lists the oscillators to be placed in the sockets, prior to the card being plugged into the socket. Table 16 SOCKET OSC 1 OSC 2 OSC 3 Oscillator placement in sockets OSCILLATOR FREQUENCY 1.544 MHz 2.048 MHz 4.096 MHz 52 MHz 44.736 MHz 1.544 MHz 2.048 MHz 40 MHz TEST CASE Unchannelized T1 on links 0 through 15 Unchannelized E1 on links 0 through 15 Unchannelized 2.048 Mbit/s H-MVIP mode Unchannelized 52 Mbit/s traffic on links 0 through 2 Unchannelized 44.736 Mbit/s traffic on links 0 through 2 Unchannelized T1 on links 16 through 31 Unchannelized E1 on links 16 through 31 SYSCLK for FREEDM-32P672
OSC 4 OSC 5
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Note: Clocks are not provisioned to the clock inputs of the FREEDM-32P672 chip simply by placing the oscillators in the appropriate sockets. Frequency selection and clock provision has to be done by means of jumpers, as mentioned in earlier sections.
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3 3.1
CONFIGURATIONS FOR THE TEST CASES Configuration for PCI Interface Test Table 17 lists the required configuration for the PCI Interface Test. Table 17 HEADER P3 P5 Configuration for the PCI Interface Test SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in row A shorted to pins in row B respectively Pins A0 through A15 shorted to pins B0 through B15 respectively Pins A16 through CONFIGURATION ACHIEVED SYSCLK connected to PCICLKO (only for 33 MHz operation) RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
P1
TFPB[3:0]
TFPB[3:0] grounded
P9 P12
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded 1.544 MHz provision to RCLK[15:0] inputs of FREEDM-32P672 1.544 MHz provision to
P11
RCLK[31:16]
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P13
TCLK[15:0]
P14
TCLK[31:16]
P7
RCL52[2:0]
P7
TCL52[2:0]
P15 P10 P2
TD RD[15:2] TD RD[31:16] TD RD[1:0]
A31 shorted to pins B16 through B31 respectively Pins A0 through A15 shorted to pins B0 through B15 respectively Pins A16 through A31 shorted to pins B16 through B31 respectively Pins B-R0, B-R1 and B-R2 shorted to pins C-R0, C-R1 and C-R2 respectively (Columns 0, 1 and 2) Pins B-T0, B-T1 and B-T2 shorted to pins C-T0, C-T1 and C-T2 respectively (Columns 0, 1 and 2) Jumpers not used Jumpers not used Jumpers not used
RCLK[31:16] inputs of FREEDM-32P672 1.544 MHz provision to TCLK[15:0] inputs of FREEDM-32P672 1.544 MHz provision to TCLK[31:16] inputs of FREEDM-32P672 1.544 MHz selection for RCLK[2:0]
1.544 MHz selection for TCLK[2:0]
No loopback on links 2 through 15 No loopback on links 16 through 31 No loopback on links 0 and 1
3.2
Configuration for unchannelized T1 loopback mode Each of the 32 transmit/receive links can be configured independently to transmit/receive unchannelized T1 data. This is done by the software. Loopback can be performed on any of these 32 links by using shorting jumpers appropriately over headers provided on the PCI card. Table 18 shows the jumper settings for performing loopback on all the 32 links. Table 18 HEADER Configuration for simultaneous loopback of T1 data on 32 links SIGNAL JUMPER CONFIGURATION ACHIEVED
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P3 P5
SYSCLK RMVCK[3:0]
SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in row A shorted to pins in row B respectively Pins A0 through A15 shorted to pins B0 through B15 respectively Pins A16 through A31 shorted to pins B16 through B31 respectively Pins A0 through A15 shorted to pins B0 through B15 respectively Pins A16 through A31 shorted to pins B16 through B31
SYSCLK connected to PCICLKO (only for 33 MHz operation) RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
P1
TFPB[3:0]
TFPB[3:0] grounded
P9 P12
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded 1.544 MHz provision to RCLK[15:0] inputs of FREEDM-32P672 1.544 MHz provision to RCLK[31:16] inputs of FREEDM-32P672 1.544 MHz provision to TCLK[15:0] inputs of FREEDM-32P672 1.544 MHz provision to TCLK[31:16] inputs of FREEDM-32P672
P11
RCLK[31:16]
P13
TCLK[15:0]
P14
TCLK[31:16]
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P7
RCL52[2:0]
P7
TCL52[2:0]
P15
TD RD[15:2]
P10
TD RD[31:16] TD RD[1:0]
P2
respectively Pins B-R0, B-R1 and B-R2 shorted to pins C-R0, C-R1 and C-R2 respectively (Columns 0, 1 and 2) Pins B-T0, B-T1 and B-T2 shorted to pins C-T0, C-T1 and C-T2 respectively (Columns 0, 1 and 2) Pins A2 through A15 shorted to pins B2 through B15 respectively Pins A16 through A31 shorted to pins B16 through B31 respectively TD0 shorted to RD0, TD1 shorted to RD1
1.544 MHz selection for RCLK[2:0]
1.544 MHz selection for TCLK[2:0]
Loopback on links 2 through 15 Loopback on links 16 through 31 Loopback on links 0 and 1
Note: 1.544 MHz oscillators should be placed in sockets OSC 1 and OSC 4. If loopback is not to be performed on each of the 32 links, jumper settings will be similar to those shown in Table 18, except for the unused RCLK, TCLK, RD and TD. Unused RCLK and TCLK should be grounded by placing jumpers over pins of columns B and C, of the unused links. Unused RD and TD need not be shorted.
3.3
Configuration for unchannelized E1 loopback mode Each of the 32 transmit/receive links can be configured independently to transmit/receive unchannelized E1 data. This is done by the software. Loopback can be performed on any of these 32 links by using shorting jumpers
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appropriately over headers provided on the PCI card. Table 18 shows the jumper settings for performing loopback on all the 32 links. Table 18 HEADER P3 P5 Configuration for simultaneous loopback of E1 data on 32 links SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in column A shorted to pins in column B respectively Pins A0 through A15 shorted to pins B0 through CONFIGURATION ACHIEVED SYSCLK connected to PCICLKO (only for 33 MHz operation) RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
P1
TFPB[3:0]
TFPB[3:0] grounded
P9
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded
P12
2.048 MHz provision to RCLK[15:0] inputs of FREEDM-32P672
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P11
P13
P14
P7
P7
P15
P10
P2
B15 respectively RCLK[31:16] Pins A16 through A31 shorted to pins B16 through B31 respectively TCLK[15:0] Pins A0 through A15 shorted to pins B0 through B15 respectively TCLK[31:16] Pins A16 through A31 shorted to pins B16 through B31 respectively RCL52[2:0] Pins B-R0, B-R1 and B-R2 shorted to pins C-R0, C-R1 and C-R2 respectively (Columns 0, 1 and 2) TCL52[2:0] Pins B-T0, B-T1 and B-T2 shorted to pins C-T0, C-T1 and C-T2 respectively (Columns 0, 1 and 2) TD RD[15:2] Pins A2 through A15 shorted to pins B2 through B15 respectively TD Pins A16 through RD[31:16] A31 shorted to pins B16 through B31 respectively TD RD[1:0] TD0 shorted to RD0, TD1 shorted to RD1
2.048 MHz provision to RCLK[31:16] inputs of FREEDM-32P672 2.048 MHz provision to TCLK[15:0] inputs of FREEDM-32P672 2.048 MHz provision to TCLK[31:16] inputs of FREEDM-32P672 2.048 MHz selection for RCLK[2:0]
2.048 MHz selection for TCLK[2:0]
Loopback on links 2 through 15
Loopback on links 16 through 31 Loopback on links 0 and 1
Note: 2.048 MHz oscillators should be placed in sockets OSC 1 and OSC 4. If loopback is not to be performed on each of the 32 links, jumper settings will be similar to those shown in Table 18, except for the unused RCLK, TCLK, RD and TD. Unused RCLK and TCLK should be grounded by placing shorting jumpers
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over pins of columns B and C, of the unused links. Unused RD and TD need not be shorted. 3.4 Configuration for 16 T1/ 16 E1 unchannelized loopback mode With 1.544 MHz oscillator placed in socket OSC 1, and 2.048 MHz oscillator placed in OSC 4, simultaneous loopback of 16 unchannelized T1 links (links 015) and 16 unchannelized E1 links (links 16-31) can be performed. The jumper settings for this loopback are shown in Table 19. Table 19 HEADER P3 P5 Configuration for 16 T1/E1 unchannelized loopback SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in column A shorted to pins in column B respectively Pins A0 through CONFIGURATION ACHIEVED SYSCLK connected to PCICLKO (only for 33 MHz operation) RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
P1
TFPB[3:0]
TFPB[3:0] grounded
P9
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded
P12
1.544 MHz provision to
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PM2352 FREEDM-32P672
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P11
P13
P14
P7
P7
P15
P10
P2
A15 shorted to pins B0 through B15 respectively RCLK[31:16] Pins A16 through A31 shorted to pins B16 through B31 respectively TCLK[15:0] Pins A0 through A15 shorted to pins B0 through B15 respectively TCLK[31:16] Pins A16 through A31 shorted to pins B16 through B31 respectively RCL52[2:0] Pins B-R0, B-R1 and B-R2 shorted to pins C-R0, C-R1 and C-R2 respectively (Columns 0, 1 and 2) TCL52[2:0] Pins B-T0, B-T1 and B-T2 shorted to pins C-T0, C-T1 and C-T2 respectively (Columns 0, 1 and 2) TD RD[15:2] Pins A2 through A15 shorted to pins B2 through B15 respectively TD Pins A16 through RD[31:16] A31 shorted to pins B16 through B31 respectively TD RD[1:0] TD0 shorted to RD0, TD1 shorted to RD1
RCLK[15:0] inputs of FREEDM-32P672 2.048 MHz provision to RCLK[31:16] inputs of FREEDM-32P672 1.544 MHz provision to TCLK[15:0] inputs of FREEDM-32P672 2.048 MHz provision to TCLK[31:16] inputs of FREEDM-32P672 1.544 MHz selection for RCLK[2:0]
1.544 MHz selection for TCLK[2:0]
Loopback on links 2 through 15 Loopback on links 16 through 31 Loopback on links 0 and 1
Note: If links 0 through 15 are to be configured for unchannelized E1 data and links 16 through 31 are to be configured for T1 data, 2.048 MHz oscillator should
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PM2352 FREEDM-32P672
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be placed in socket OSC 1, whereas 1.544 MHz oscillator should be placed in OSC 4. 3.5 Configuration for unchannelized 52 Mbit/s Links 0 through 2 can be configured for supporting 52 Mbit/s data. The jumper settings for simultaneous loopback of 52 Mbit/s on links 0 through 2, is shown in Table 20. Table 20 HEADER P3 P5 Simultaneous loopback of unchannelized 52 Mbit/s data on links 0 through 2 SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and A Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in column A shorted to pins in column B respectively Pins Ay shorted to pins By CONFIGURATION ACHIEVED SYSCLK set to 40 MHz RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
P1
TFPB[3:0]
TFPB[3:0] grounded
P9
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded
P12
52 MHz provision to RCLK[2:0] inputs of FREEDM-32P672.
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PM2352 FREEDM-32P672
ISSUE 1
DEVELOPMENT KIT BOARD USER MANUAL
P11
P13
P14
P7
P7
P15 P10 P2
respectively, where y = link to be operated at 52 MHz The pins Bz shorted to pins Cz where z = link to be disabled RCLK[31:16] Pins C16 through C31 shorted to pins B16 through B31 respectively TCLK[15:0] Pins Ay shorted to pins By respectively, where y = link to be operated at 52Mhz. The pins Bz shorted to pins Cz where z = link to be disabled TCLK[31:16] Pins C16 through C31 shorted to pins B16 through B31 respectively RCL52[2:0] Pins A-R0, A-R1 and A-R2 shorted to pins B-R0, B-R1 and B-R2 respectively (Columns 0, 1 and 2) TCL52[2:0] Pins B-T0, B-T1 and B-T2 shorted to pins A-T0, A-T1 and A-T2 respectively (Columns 0, 1 and 2) TD RD[15:2] Pin A2 shorted to pin B2 respectively TD Jumpers not used RD[31:16] TD RD[1:0] TD0 shorted to RD0, TD1 shorted
(select 2 links to provision, disable the third)
RCLK[31:16] grounded
52 MHz provision to TCLK[2:0] inputs of FREEDM-32P672. ( select 2 links to provision and disable the third)
TCLK[31:16] grounded
52 MHz selection for RCLK[2:0]
52 MHz selection for TCLK[2:0]
Loopback on link 2 No loopback on links 16 through 31 Loopback on links 0 and 1
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PM2352 FREEDM-32P672
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to RD1 Note 1: All unused RCLK and TCLK should be grounded, by placing shorting jumpers over pins of columns B and C, of the unused links. Shorting jumpers need not be placed over receive/transmit links 3 through 31 (RD[31:3] and TD[31:3]). If not all three RCLK and TCLK are used, unused RCLK and TCLK should be grounded. Note 2: If simultaneous cross-connect of data on links 0 and 1 is to be performed, TD0 should be shorted to RD1, whereas TD1 should be shorted to RD0, on header P2. Note 3: Software support is provided for 52Mbit/s data loopback on only 2 of the 3 possible links, RCLK and TCLK inputs for the third link should be disabled. Also, SYSCLK can be connected to PCICLKO output of the FREEDM-32P672 chip, provided that PCI frequency is 33 MHz. 3.6 Configuration for unchannelized Mixed DS3/T1/E1 data loopback Links 0 through 2 can be configured for supporting DS-3 data. The jumper settings for simultaneous loopback of Mixed DS3/T1/E1, is shown in Table 21 Table 21 HEADER P3 P5 Simultaneous loopback of unchannelized Mixed DS3/T1/E1 data SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and A Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and CONFIGURATION ACHIEVED SYSCLK set to 40 MHz RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
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PM2352 FREEDM-32P672
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P1
TFPB[3:0]
P9
RFP8B & TFP8B RCLK[15:0]
P12
P11
RCLK[31:16]
P13
TCLK[15:0]
P14
TCLK[31:16]
A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in column A shorted to pins in column B respectively Pins Ay shorted to pins By respectively, where y = link to be operated at DS3, T1 or E1. The pins Bz shorted to pins Cz where z = link to be disabled Pins Ay shorted to pins By respectively, where y = link to be operated at T1 or E1. The pins Bz shorted to pins Cz where z = link to be disabled Pins Ay shorted to pins By respectively, where y = link to be operated at DS3, T1 or E1. The pins Bz shorted to pins Cz where z = link to be disabled Pins Ay shorted to pins By respectively, where y = link to be operated at T1 or E1. The pins Bz
TFPB[3:0] grounded
RFP8B and TFP8B grounded
DS3 provision to RCLK[2:0] inputs of FREEDM-32P672. T1/E1 clocks connected to selective links for Mixed DS3/T1/E1 operation
Selected Links enabled for T1/E1 operation (Mixed mode)
DS3 provision to TCLK[2:0] inputs of FREEDM-32P672. T1/E1 clocks connected to selective links for Mixed DS3/T1/E1 operation
Selected Links enabled for T1/E1 operation (Mixed mode)
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PM2352 FREEDM-32P672
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P7
RCL52[2:0]
P7
TCL52[2:0]
P15
TD RD[15:2]
P10
TD RD[31:16]
P2
TD RD[1:0]
shorted to pins Cz where z = link to be disabled Pins A-Ry shorted to pins B-Ry, respectively, where y [y = 0,1 or 2] is the link to be operated at DS3. Pins B-Rz shorted to C-Rz where z = links not used for DS3 Pins A-Ty shorted to pins B-Ty, respectively, where y [y = 0,1 or 2] is the link to be operated at DS3. Pins B-Tz shorted to C-Tz where z = links not used for DS3 Pins Ay shorted to pins By respectively, where y = link to be operated at DS3/T1/E1 Pins Ay shorted to pins By respectively, where y = link to be operated at T1/E1 TDy shorted to RDy respectively, where y = link to be operated at DS3/T1/E1
DS3 selection for RCLK[2:0] (One of the links 0, 1 or 2 is operated at DS3 rate)
DS3 selection for TCLK[2:0] (One of the links 0, 1 or 2 is operated at DS3 rate)
Loopback on selected links
Loopback on selected links
Loopback on selected links
Note 1: All unused RCLK and TCLK should be grounded, by placing shorting jumpers over pins of columns B and C, of the unused links. Shorting jumpers need not be placed over unused receive/transmit links.
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PM2352 FREEDM-32P672
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Note 2: The aggregate instantaneous clock rate over all 32 possible links is limited to 64 MHz. 3.7 Configuration for unchannelized 2.048 Mbit/s H-MVIP data loopback One or more link groups can be configured to receive/transmit unchannelized 2.048 Mbit/s H-MVIP data. The jumper settings for performing loopback of 2.048 Mbit/s H-MVIP data on all the 32 links, is shown in Table 22. Table 22 HEADER P3 P5 Configuration for unchannelized 2.048 Mbit/s H-MVIP data loopback SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins A0, A1, A2 and A3 respectively Pins B0, B1, B2 and B3 shorted to pins A0, A1, A2 and A3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins C0, C1, C2 and C3 shorted to pins B0, B1, B2 and B3 respectively Pins C0, C1, C2 and C3 shorted to pins B0, B1, B2 and B3 respectively Pins in column A shorted to pins in column B respectively Pins C0 through CONFIGURATION ACHIEVED SYSCLK connected to PCICLKO (only for 33 MHz operation) 4.096 MHz provision to RMVCK inputs of FREEDM-32P672 4.096 MHz provision to TMVCK inputs of FREEDM32P672 RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] pulled high
P6
TMVCK[3:0]
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
P1
TFPB[3:0]
TFPB[3:0] pulled high
P9
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded
P12
RCLK[15:0] grounded
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM2352 FREEDM-32P672
ISSUE 1
DEVELOPMENT KIT BOARD USER MANUAL
P11
RCLK[31:16]
P13
TCLK[15:0]
P14
TCLK[31:16]
P7 P7 P15
RCL52[2:0] TCL52[2:0] TD RD[15:2]
P10
TD RD[31:16] TD RD[1:0]
P2
C15 shorted to pins B0 through B15 respectively Pins C16 through C31 shorted to pins B16 through B31 respectively Pins C0 through C15 shorted to pins B0 through B15 respectively Pins C16 through C31 shorted to pins B16 through B31 respectively No shorting jumper placed on this header No shorting jumper placed on this header Pins A2 through A15 shorted to pins B2 through B15 respectively Pins A16 through A31 shorted to pins B16 through B31 respectively TD0 shorted to RD0, TD1 shorted to RD1
RCLK[31:16] grounded
TCLK[15:0] grounded
TCLK[31:16] grounded
Loopback on links 2 through 15 Loopback on links 16 through 31 Loopback on links 0 and 1
Note 1: 4.096 MHz oscillator should be placed in socket OSC 2. Note 2: If all the link-groups are not configured for unchannelized 2.048 Mbit/s HMVIP mode, unused RMVCK and TMVCK should be grounded. No shorting jumpers should be used over unused RD and TD. For example, if link-group 0 alone is configured for unchannelized 2.048 Mbit/s H-MVIP mode, 4.096 MHz clock should be provided to RMVCK[0] only. Hence, on header P5, pin B0 should be shorted to A0, whereas pins B1, B2 and B3 should be shorted to pins C1, C2 and C3 respectively (i.e. RMVCK[3:1] grounded). Also, pins corresponding to TD[31:8] and RD[31:8] are not shorted to each other.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM2352 FREEDM-32P672
ISSUE 1
DEVELOPMENT KIT BOARD USER MANUAL
3.8
Configuration for unchannelized 8.192 Mbit/s H-MVIP data loopback Unchannelized H-MVIP data at 8.192 Mbit/s can be transmitted/received by the FREEDM-32P672 chip on links 4m (0m7) only. The configuration for loopback of 8.192 Mbit/s H-MVIP data on links 4m is shown in Table 23. Table 23 HEADER P3 P5 Configuration for unchannelized 8.192 Mbit/s H-MVIP data loopback SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Wire to board connector plugged into pins of rows C and D Wire to board connector plugged into pins of rows A and B Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in column C shorted to pins in column B respectively Pins C0 through C15 shorted to pins CONFIGURATION ACHIEVED SYSCLK connected to PCICLKO (only for 33 MHz operation) RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK [3:0] grounded
P4
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
16.384 MHz provision to RMV8DC &TMV8DC 4.096 MHz provision to RMV8FPC & TMV8FPC RFPB[3:0] grounded
P4
P8
P1
TFPB[3:0]
TFPB[3:0] grounded
P9
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B pulled high
P12
RCLK[15:0] grounded
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM2352 FREEDM-32P672
ISSUE 1
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P11
RCLK[31:16]
P13
TCLK[15:0]
P14
TCLK[31:16]
P7 P7 P15
RCL52[2:0] TCL52[2:0] TD RD[15:2]
P10
TD RD[31:16]
P2
TD RD[1:0]
B0 through B15 respectively Pins C16 through C31 shorted to pins B16 through B31 respectively Pins C0 through C15 shorted to pins B0 through B15 respectively Pins C16 through C31 shorted to pins B16 through B31 respectively No shorting jumper placed on this header No shorting jumper placed on this header Pins A4, A8 and A12 shorted to pins B4, B8 and B12 respectively Pins A16, A20, A24 and A28 shorted to pins B16, B20, B24 and B28 respectively TD0 shorted to RD0
RCLK[31:16] grounded
TCLK[15:0] grounded
TCLK[31:16] grounded
Loopback on links 4, 8 and 12
Loopback on links 16, 20, 24 and 28
Loopback on link 0
Note : If all the links in the group 4m (0m7), are not used, the unused TD and RD pins should not be shorted. For example, if only link 0 is used for 8.192 Mbit/s H-MVIP mode, then only RD0 and TD0 should be shorted by a jumper. The remaining RD and TD header pins should not be shorted. 3.9 BERT Signal Verification Configure links 0 and 2 for unchannelized 52 MHz (or 1.544 MHz or 2.048 MHz) mode. Hardware provision for 52 MHz (or 1.544 MHz or 2.048 MHz) clock at RCLK [0] and TCLK[0] of the FREEDM-32P672 chip is made for BERT signal
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PM2352 FREEDM-32P672
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verification test. Also, RBCLK and TBCLK are shorted respectively to RCLK[2] and TCLK[2]. Loopback of data on link 0 is enabled in hardware. Hardware configuration is done by shorting header pins corresponding to TBD and RBD, with header pins corresponding to TD[2] and RD[2], respectively. The idea is to make link 2 to emulate the BERT data, which may then be looped back externally by link 0. The jumper settings for BERT signal verification test are shown in Table 24. Table 24 HEADER P3 P5 Configuration for BERT signal verification test SIGNAL SYSCLK RMVCK[3:0] JUMPER SETTINGS Jumper over pins B and C Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins B0, B1, B2 and B3 shorted to pins C0, C1, C2 and C3 respectively Pins in row C shorted to pins in row D respectively Pins in row A shorted to pins in row B respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins A0, A1, A2 and A3 shorted to pins B0, B1, B2 and B3 respectively Pins in column A shorted to pins in column B respectively Pins A0 and A2 shorted to pins B0 and B2 CONFIGURATION ACHIEVED SYSCLK connected to PCICLKO (only for 33 MHz operation) RMVCK[3:0] grounded
P6
TMVCK[3:0]
TMVCK[3:0] grounded
P4 P4 P8
RMV8DC & TMV8DC RMV8FPC & TMV8FPC RFPB[3:0]
RMV8DC &TMV8DC grounded RMV8FPC & TMV8FPC grounded RFPB[3:0] grounded
P1
TFPB[3:0]
TFPB[3:0] grounded
P9
RFP8B & TFP8B RCLK[15:0]
RFP8B and TFP8B grounded
P12
1.544 MHz provision to RCLK[0] and RCLK[2] inputs of FREEDM-32P672
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PM2352 FREEDM-32P672
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P11
RCLK[31:16]
P13
TCLK[15:0]
P14
TCLK[31:16]
P7
RCL52[2:0]
P7
TCL52[2:0]
P15
TD RD[15:2]
P10 P2
TD RD[31:16] TD RD[1:0]
respectively; Bx shorted to Cx where x=(1,3 to 15) Pins C16 through C31 shorted to pins B16 through B31 respectively Pins A0 and A2 shorted to pins B0 and B2 respectively; Bx shorted to Cx where x=(1,3 to 15) Pins C16 through C31 shorted to pins B16 through B31 respectively Pin B-R2 shorted to RBCLK. Pin B-R0 shorted to pin C0. Pin B-T2 shorted to TBCLK Pin B-T0 shorted to pin C0. TBD shorted to TD[2] RBD shorted to RD[2] Jumpers not used TD0 shorted to RD0
RCLK[31:16] grounded
1.544 MHz provision to TCLK[0] and TCLK[2] inputs of FREEDM-32P672
TCLK[2] grounded
RBCLK shorted to RCLK[2]
TBCLK shorted to TCLK[2]
BERT Emulation by link 2
No loopback on links 16 through 31 Loopback on link 0
Note : 1.544 MHz clock is used on links 0 and 2 for this particular test case.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM2352 FREEDM-32P672
ISSUE 1
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4
HOW TO PROCEED WITH THE TEST CASES Prior to plugging the card into the slot, the user has to place all the oscillators in the appropriate sockets as mentioned in section 2.17. The user also has to select the voltage source as mentioned in section 2. Tables in section 3 of the manual only mention the jumper settings for each test case. The user should go through section 2 to know how the jumpers are placed over the headers. The bitmap image of the Development Kit, provided in section 2, can be used to locate the positions of the headers. Ground marks are provided on the PCB to indicate the position of ground pins on the various headers. These ground marks are aligned with the rows (or columns) carrying only ground pins.
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PM2352 FREEDM-32P672
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NOTES
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PM2352 FREEDM-32P672
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-2001840 Issue date: December 2000
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